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Codax2000 / fir-cnn-rtl

SystemVerilog for implementing MATLAB neural net onto Xilinx RFSoC.
MIT License
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Update toplevel with new module ports #62

Closed Codax2000 closed 1 year ago

Codax2000 commented 1 year ago

Check new ports for fc_output_layer, remove fifo from datapath, check port names, add new ready out port

Codax2000 commented 1 year ago

Rerun top-level testbench, write assertion-based testbench and python script for post-synthesis testing

Codax2000 commented 1 year ago

image

Current latency: As predicted, ~31 us, assuming a continuous stream of input data

Codax2000 commented 1 year ago

Synthesis completing image

Codax2000 commented 1 year ago

Critical warning in previous comment is that incremental synthesis is not suitable, so OK to ignore

Codax2000 commented 1 year ago

Synthesis timing report: image