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Codax2000 / fir-cnn-rtl

SystemVerilog for implementing MATLAB neural net onto Xilinx RFSoC.
MIT License
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Debug FPGA implementation #66

Closed Codax2000 closed 1 year ago

Codax2000 commented 1 year ago

FPGA says that too many DSP slices are being used, must reduce to around 4,000