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Codax2000 / fir-cnn-rtl

SystemVerilog for implementing MATLAB neural net onto Xilinx RFSoC.
MIT License
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Debug FPGA Deployment #78

Closed Codax2000 closed 1 year ago

Codax2000 commented 1 year ago

Test Case 1 Test Case 2 Test Case 3

Codax2000 commented 1 year ago

Compare to top 3 cases in actual outputs file. Start signal may be buggy, but is fully functional. Compare to expected values from simulation: image