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Codax2000 / fir-cnn-rtl

SystemVerilog for implementing MATLAB neural net onto Xilinx RFSoC.
MIT License
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finalize FPGA project flow #82

Closed Codax2000 closed 1 year ago

Codax2000 commented 1 year ago

Add macros and sample testbenches with waveforms, ensure .mem files are in the right place and that script is updated.