The functions to_bool and to_sl don't exist in the generated VHDL package.
Example
//> using scala 3.4.0
//> using dep io.github.dfianthdl::dfhdl::0.4.3+12-a64c002c-SNAPSHOT
//> using plugin io.github.dfianthdl:::dfhdl-plugin:0.4.3+12-a64c002c-SNAPSHOT
//> using option -deprecation -language:implicitConversions
import dfhdl.*
class TypeConvertIssue() extends RTDesign:
val a = Bit <> IN
val b = Bit <> IN
val c = UInt(8) <> IN
val d = Bit <> OUT
val e = Bit <> OUT
d := 0
if (c < 3 && b)
d := 1
e := 0
if (b && c < 3)
e := 1
@main def main =
TypeConvertIssue().compile
Output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.TypeConvertIssue_pkg.all;
entity TypeConvertIssue is
port (
a : in std_logic;
b : in std_logic;
c : in unsigned(7 downto 0);
d : out std_logic;
e : out std_logic
);
end TypeConvertIssue;
architecture TypeConvertIssue_arch of TypeConvertIssue is
begin
process (all)
begin
d <= '0';
if (c < 8d"3") and to_bool(b) then d <= '1'; -- uses to_bool which does not exist
end if;
e <= '0';
if b and to_sl(c < 8d"3") then e <= '1'; -- uses to_sl which does not exist
end if;
end process;
end TypeConvertIssue_arch;
Description
The functions to_bool and to_sl don't exist in the generated VHDL package.
Example
Output