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DFiantHDL / DFHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
https://dfianthdl.github.io/
GNU Lesser General Public License v3.0
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asic dataflow dataflow-programming fpga hdl

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DFiant HDL

Build Status dfhdl Scala version support Discord Chat Scala Steward badge

Welcome to the DFiant hardware description language (DFHDL) repository!

DFHDL is a dataflow HDL and is embedded as a library in the Scala programming language. DFiant enables timing-agnostic and device-agnostic hardware description by using dataflow firing rules as logical constructs, coupled with modern software language features (e.g., inheritance, polymorphism, pattern matching) and classic HDL features (e.g., bit-accuracy, input/output ports). Additionally, DFHDL integrates two additional levels of hardware description abstractions: register-transfer (RT), which is equivalent to languages like Chisel and Amaranth; and event-driven (ED), which is equivalent to Verilog and VHDL.

Read the documentation: https://dfianthdl.github.io/

Acknowledgement

Previous version of this work (simply called "DFiant" at the time) has been supported by EU H2020 ICT project LEGaTO, contract #780681.