to_slv function missing for std_logic

[MartinC45]

Description

Generated VHDL uses the function to_slv to convert b(0), but the function does not exist for std_logic.

The following function is needed

-- in package header
function to_slv(A : std_logic) return std_logic_vector;

-- in package body
function to_slv(A : std_logic) return std_logic_vector is
begin
  if A = '1' then 
    return "1";
  else
    return "0";
  end if;
end;

Example

class StdLogicConvIssue() extends RTDesign:
    val a = Bits(10) <> IN
    val e = Bits(10) <> OUT

    e := (a(0), a(3), b"0", false.bit, b"000000")

Output

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.StdLogicConvIssue_pkg.all;

entity StdLogicConvIssue is
port (
  a : in  std_logic_vector(9 downto 0);
  e : out std_logic_vector(9 downto 0)
);
end StdLogicConvIssue;

architecture StdLogicConvIssue_arch of StdLogicConvIssue is
begin
  process (all)
  begin
    e <= to_slv(a(0)) & to_slv(a(3)) & "0" & "0" & 6x"00"; -- problem here
  end process;
end StdLogicConvIssue_arch;