More RT to ED and VHDL/Verilog printing improvements - Githubissues

DFiantHDL / DFHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

https://dfianthdl.github.io/

GNU Lesser General Public License v3.0

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More RT to ED and VHDL/Verilog printing improvements #132

Closed soronpo closed 5 months ago

soronpo commented 5 months ago

Fix ToED stage for match select
Fix #131
Add UART Tx Example
Consistent printing of types in Verilog/VHDL