Trying to index and assign to a Bits(1) fails with the error below.
Example
import dfhdl.*
class Width0Issue(val width : Int <> CONST) extends RTDesign:
val d = Bit <> IN
val a = Bits(width) <> VAR
a(0) := d // works only when width > 1
// a := d // works like this when width = 1
@main def main =
Width0Issue(1).compile
Width0Issue(2).compile // works
DFiant HDL elaboration error!
Position: ~/Documents/DFHDL_examples/Issues.scala:6:5 - 6:9
Hierarchy: Width0Issue
Operation: `apply`
Message: Unsigned value width must be positive, but found: 0
Description
Trying to index and assign to a Bits(1) fails with the error below.
Example