Verilog doesn't use arithmetic right shift for SInt

[MartinC45]

Description

>> is translated to >> in the case of SInt, but it should be >>>.

Example

import dfhdl._
class VerilogSRA() extends RTDesign:
    val a = SInt(10) <> IN
    val b = SInt(10) <> VAR

    b := a >> 1

@main def main = 
    VerilogSRA().compile

Output

module VerilogSRA(
  input wire logic signed [9:0] a
);
  logic signed [9:0] b;
  always @(*)
  begin
    b = a >> 1; \\ this is a logical right shift, which doesn't keep the sign bit
  end
endmodule

[soronpo]

Nice catch. I'm again and again amazed as to how Verilog manage to lead the industry. So many pitfalls.