Error in VHDL code gen when vectors are part of struct

Example

import dfhdl._

case class EmbeddedArray (
    a : Bits[8]X(3) <> VAL
) extends Struct

class StructArrayIssue() extends RTDesign:
    val a = Bit <> IN
    val e = EmbeddedArray <> VAR
    e.a(0)(0) := a

given options.CompilerOptions.Backend = backends.vhdl.v2008

@main def main = 
   StructArrayIssue().compile

Output

Exception in thread "main" java.lang.IllegalArgumentException: Unsupported member for this RTPrinter.
        at dfhdl.compiler.stages.vhdl.VHDLPrinter.unsupported(VHDLPrinter.scala:17)
        at dfhdl.compiler.stages.vhdl.VHDLValPrinter.csBitsToType(VHDLValPrinter.scala:116)
        at dfhdl.compiler.stages.vhdl.VHDLValPrinter.csBitsToType$(VHDLValPrinter.scala:8)
        at dfhdl.compiler.stages.vhdl.VHDLPrinter.csBitsToType(VHDLPrinter.scala:8)
        at dfhdl.compiler.stages.vhdl.VHDLTypePrinter.$anonfun$5(VHDLTypePrinter.scala:156)
        at scala.collection.StrictOptimizedIterableOps.map(StrictOptimizedIterableOps.scala:100)
        at scala.collection.StrictOptimizedIterableOps.map$(StrictOptimizedIterableOps.scala:87)
        at scala.collection.immutable.ListMap.map(ListMap.scala:43)
        at dfhdl.compiler.stages.vhdl.VHDLTypePrinter.csDFStructConvFuncsBody(VHDLTypePrinter.scala:156)
        at dfhdl.compiler.stages.vhdl.VHDLTypePrinter.csDFStructConvFuncsBody$(VHDLTypePrinter.scala:10)
        at dfhdl.compiler.stages.vhdl.VHDLPrinter.csDFStructConvFuncsBody(VHDLPrinter.scala:8)
        at dfhdl.compiler.stages.vhdl.VHDLOwnerPrinter$$anon$3.applyOrElse(VHDLOwnerPrinter.scala:58)
        at dfhdl.compiler.stages.vhdl.VHDLOwnerPrinter$$anon$3.applyOrElse(VHDLOwnerPrinter.scala:58)
        at scala.collection.Iterator$$anon$7.hasNext(Iterator.scala:525)
        at scala.collection.IterableOnceOps.addString(IterableOnce.scala:1245)
        at scala.collection.IterableOnceOps.addString$(IterableOnce.scala:1241)
        at scala.collection.AbstractIterable.addString(Iterable.scala:933)
        at scala.collection.IterableOnceOps.mkString(IterableOnce.scala:1191)
        at scala.collection.IterableOnceOps.mkString$(IterableOnce.scala:1189)
        at scala.collection.AbstractIterable.mkString(Iterable.scala:933)
        at scala.collection.IterableOnceOps.mkString(IterableOnce.scala:1204)
        at scala.collection.IterableOnceOps.mkString$(IterableOnce.scala:1204)
        at scala.collection.AbstractIterable.mkString(Iterable.scala:933)
        at dfhdl.compiler.stages.vhdl.VHDLOwnerPrinter.csArchitectureDcl(VHDLOwnerPrinter.scala:59)
        at dfhdl.compiler.stages.vhdl.VHDLOwnerPrinter.csArchitectureDcl$(VHDLOwnerPrinter.scala:10)
        at dfhdl.compiler.stages.vhdl.VHDLPrinter.csArchitectureDcl(VHDLPrinter.scala:8)
        at dfhdl.compiler.stages.vhdl.VHDLOwnerPrinter.csDFDesignBlockDcl(VHDLOwnerPrinter.scala:89)
        at dfhdl.compiler.stages.vhdl.VHDLOwnerPrinter.csDFDesignBlockDcl$(VHDLOwnerPrinter.scala:10)
        at dfhdl.compiler.stages.vhdl.VHDLPrinter.csDFDesignBlockDcl(VHDLPrinter.scala:8)
        at dfhdl.compiler.printing.Printer.csFile(Printer.scala:150)
        at dfhdl.compiler.printing.Printer.csFile$(Printer.scala:19)
        at dfhdl.compiler.stages.vhdl.VHDLPrinter.csFile(VHDLPrinter.scala:8)
        at dfhdl.compiler.printing.Printer.$anonfun$1(Printer.scala:170)
        at scala.collection.immutable.List.map(List.scala:246)
        at dfhdl.compiler.printing.Printer.printedDB(Printer.scala:172)
        at dfhdl.compiler.printing.Printer.printedDB$(Printer.scala:19)
        at dfhdl.compiler.stages.vhdl.VHDLPrinter.printedDB(VHDLPrinter.scala:8)
        at dfhdl.compiler.stages.BackendCompiler.compile(BackendCompiler.scala:19)
        at dfhdl.compiler.stages.BackendCompiler.compile$(BackendCompiler.scala:8)
        at dfhdl.backends$vhdl.compile(backends.scala:23)
        at dfhdl.compiler.stages.StagedDesign$.compile(StagedDesign.scala:13)
        at dfhdl.ops$package$.compile(ops.scala:10)
        at project$package$.main(project.scala:51)
        at main.main(project.scala:27)

DFiantHDL / DFHDL

Error in VHDL code gen when vectors are part of struct #141

Example

Output