Double struct declaration for VHDL

[MartinC45]

Description

Structs that are used in the port declaration are declared in the package, whereas structs used internally are declared in the architecture, which leads to double struct declaration.

Example

case class InStruct (
    a : Bit <> VAL,
    b : Bit <> VAL
) extends Struct

class DoubleStructDecl() extends RTDesign():
    val sin = InStruct <> IN
    val svar = InStruct <> VAR
    svar := sin

given options.CompilerOptions.Backend = backends.vhdl.v2008

@main def main = 
   DoubleStructDecl().compile

Output

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.DoubleStructDecl_pkg.all;

entity DoubleStructDecl is
port (
  clk : in std_logic;
  rst : in std_logic;
  sin : in t_struct_InStruct -- declared in the package
);
end DoubleStructDecl;

architecture DoubleStructDecl_arch of DoubleStructDecl is
  type t_struct_InStruct is record -- redeclared here
    a : std_logic;
    b : std_logic;
  end record;
  signal svar : t_struct_InStruct;
begin
  process (all)
  begin
    svar <= sin;
  end process;
end DoubleStructDecl_arch;