This project is a Vivado demo using the Arty A7 100T's, Pmod Ports and the Pmod VGA written in VHDL. The Pmod VGA is controlled by the Arty A7 through Pmod ports JB and JC. When programmed onto the board, a bouncing box and many test pattern bars are displayed on a connected VGA monitor. The screen resolution is configurable through HDL code.
You may want to change the display resolution if your VGA monitor does not support 1080p, or you want to modify the demo for a specific application. To select a different display resolution, select the appropriate set of Sync Generation constants for your target resolution from the list starting at line 47 of top.vhd. Uncomment the ten corresponding constants, FRAME_WIDTH through V_POL, and comment the default versions of those same constants. The default resolution is 1920×1080 @ 60Hz. Next, select Project Manager in the Flow Navigator. In the Hierarchy tab of the Sources box, expand top under Design Sources and double click on clk_div_inst. Change the clk_out1 requested frequency to the required pxl_clk frequency specified in the selected resolution's Sync Generation comment block. Select Ok, then Generate in the Generate Output Products dialog that pops up. To reprogram your board with the new hardware, return to Step 2.
This demo can be used as a basis for other projects, either by adding sources included in the demo's release to those projects, or by modifying the sources in the release project.
Check out the Arty A7-100T's Resource Center to find more documentation, demos, and tutorials.
For technical support or questions, please post on the Digilent Forum.
For more information on how this project is version controlled, refer to the Digilent Vivado Scripts Repository