This repository contains the files used by Vivado IP Integrator to support Digilent system boards. They include board interfaces, preset configurations for the IP that can connect to those interfaces, and the constraints required to connect the pins of those interfaces to physical FPGA pins. Memory Interface Generator (MIG) project files are also included for non-Zynq boards which can be used to configure the Xilinx MIG IP for use with Microblaze systems.
The old folder is for use with Vivado versions 2014.4 and below. The new folder covers Vivado 2015.x and above.
Installation instructions for the new files can be found in Section 3 of the Installing Vivado, Vitis, and Digilent Board Files guide on Digilent Refeernce.
Installation instructions for the old files can be found in the Installing Vivado Board Files for Digilent Boards (Legacy) guide on the Digilent Wiki.