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IObundle
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iob-soc
RISC-V System on Chip Template
MIT License
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86
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Update py2hwsw version
#976
arturum1
closed
2 days ago
0
Update README; Rename `PY2HWSW_PATH` to `PY2HWSW_ROOT`.
#975
arturum1
closed
1 week ago
0
If gen2
#974
jjts
closed
2 weeks ago
0
Merge branch 'main' of github.com:IObundle/iob-soc into if_gen2
#973
arturum1
closed
2 weeks ago
0
[ipxact_gen] added data_if to core and file name
#972
AndreMerendeira
closed
2 weeks ago
0
Update py2hwsw version
#971
arturum1
closed
2 weeks ago
0
fix(ipxact): Ignore confs with doc_only=True
#970
arturum1
closed
3 weeks ago
0
Add support for doc_only attribute in confs and swregs
#969
arturum1
closed
3 weeks ago
0
Update py2hwsw version
#968
arturum1
closed
3 weeks ago
0
Merge branch 'main' of IObundle/iob-soc into if_gen2; Update py2hwsw version.
#967
arturum1
closed
3 weeks ago
0
fix(CDC): axistream in
#966
P-Miranda
opened
4 weeks ago
0
feat(nco, axis): fix NCO, AXIS IN, AXIS OUT
#965
P-Miranda
closed
3 weeks ago
0
Ipxact fix
#964
AndreMerendeira
closed
4 weeks ago
0
fix(regfile): replace regfile_t2p by regfile_at2p
#963
P-Miranda
closed
1 month ago
0
Update py2 version; Add `README.md`.
#962
arturum1
closed
1 month ago
0
fix(fpga): connect rstn wire to 1st interface
#961
P-Miranda
closed
1 month ago
0
feat(reset): improve reset sync
#960
P-Miranda
closed
1 month ago
2
Improve `default.nix` to import the one from py2hwsw
#959
arturum1
closed
1 month ago
0
Move lib modules to py2hwsw repo; Fix git clone of py2hwsw submodules; Add ci.yml test to check compliance with REUSE Specification.
#958
arturum1
closed
1 month ago
0
fix(xsim): variables for remote simulation
#957
P-Miranda
closed
1 month ago
2
Add SPDX license headers; Refactor iob_soc; Remove unneeded `original_name` and `name` attributes; Fix append of lists from `iob_system` child cores.
#956
arturum1
closed
1 month ago
0
Pass `iob_soc` attributes via python parameters to `iob_system` parent.
#955
arturum1
closed
1 month ago
0
[ipxact] fixed params replacement
#954
AndreMerendeira
closed
1 month ago
0
Move `iob_soc` to lib and rename it to `iob_system`; Replace `axil` peripheral cbus by `iob` interface.
#953
arturum1
closed
1 month ago
0
fix simulation (icarus) and synthesis (yosys) errors
#952
jjts
opened
2 months ago
1
Add needed suffixes to accomodate new Py2HWSW syntax
#951
agrevin
closed
2 months ago
1
Update portnames to new py2 syntax
#950
agrevin
closed
2 months ago
0
Support multiple clocks for Verilator Simulation
#949
P-Miranda
closed
2 months ago
1
iob_r input/output signals {iob_r_data_i/o} should be renamed do data_i/o
#948
AndreMerendeira
closed
2 months ago
6
clang format
#947
jjts
opened
2 months ago
1
Create `iob_axil_split` module; Use single `axi2axil` bridge; Use `axil` interface for peripherals. Move bootrom to address 0x40000000.
#946
arturum1
closed
2 months ago
0
Add VexRiscv CPU; Use system structure similar to iob_soc_opencryptolinux.
#945
arturum1
closed
2 months ago
0
Create iob_rom_2p
#944
arturum1
closed
2 months ago
0
Ram2
#943
mbot27
closed
2 months ago
0
iob_reset_sync should be called iob_areset_sync
#942
AndreMerendeira
closed
1 month ago
4
module iob_ram_2p generated with py2hwsw
#941
mbot27
closed
2 months ago
0
Add missing regs in lib modules; Add `PY2HWSW_PATH` environment variable; Update py2hwsw.
#940
arturum1
closed
2 months ago
0
module iob_ram_sp_generated with py2hwsw
#939
mbot27
closed
2 months ago
0
Create iob_rom_2p
#938
Edw590
closed
2 months ago
2
Refactor iob-soc wrappers; Add `axi_interconnect_wrapper` module; Generate bootrom with py2.
#937
arturum1
closed
2 months ago
0
Merge Revamp2; Refactor iob-soc.
#936
arturum1
closed
3 months ago
0
Merge revamp2
#935
arturum1
closed
3 months ago
1
Merge with if_gen2
#934
Edw590
closed
3 months ago
1
Merge with if_gen2
#933
Edw590
closed
3 months ago
0
Rename fpga folders; Refactor kintex wrapper; Fix bugs and clean target; Update py2hwsw.
#932
arturum1
closed
3 months ago
0
Update bootrom with new py2hwsw csrs.
#931
arturum1
closed
3 months ago
0
Fix need for ADDR-4 on preboot.S
#930
Edw590
closed
3 months ago
0
Update iob_axistream cores; Inherit confs from regfileif instantiator; Merge 'main' branch.
#929
arturum1
closed
3 months ago
0
Use DDR_ADDR_W for DDR instead
#928
Edw590
closed
3 months ago
0
Ram
#927
mbot27
closed
2 months ago
2
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