I am very sure that cpuset is correct. The issue (I think) comes from looping through cpuset (a lot of cycles) that the timer isn't clocked for a while, so the FIFO isnt clocked etc.
This can be fixed by simply not hle cpuset for now.
Another fix can be stepping the scheduler in cpuset.
This happens when hle cpuset.
I am very sure that cpuset is correct. The issue (I think) comes from looping through cpuset (a lot of cycles) that the timer isn't clocked for a while, so the FIFO isnt clocked etc.
This can be fixed by simply not hle cpuset for now.
Another fix can be stepping the scheduler in cpuset.