always allow changes to dma len,src,dst on dma control write, even if the channel doesnt get enabled (0 -> 1 enable transition).
delay starting the dma by at least 3 cycles, relative to the current time. meaning if a store-word instruction happens, that write takes 2 cycles, then i have to delay the dma by scheduler.current_cycles + sheduler.elapsed + 3.
only start an immediate dma transfer on the enable bit transitioning from 0 -> 1.
i think (1) is a false positive. 2 and 3 maybe both be correct fixes (although it only needs one of them). immediate dma is supposed to be delayed by 2-3(?) cycles.
https://user-images.githubusercontent.com/47043333/193606571-82095135-bf25-4df4-bed7-363bdd191c03.mp4
i have found 3 possible fixes:
i think (1) is a false positive. 2 and 3 maybe both be correct fixes (although it only needs one of them). immediate dma is supposed to be delayed by 2-3(?) cycles.