JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
https://github.com/JulianKemmerer/PipelineC/wiki
GNU General Public License v3.0
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How to combine multiple clock domains in a single function? #118

Open JulianKemmerer opened 2 years ago

JulianKemmerer commented 2 years ago

Ratioed clock domains are sorta like initiation interval != 1? maybe?

Useful for DSP ~double pumping kind of things?

my_func()
{
  #pragma RATE 2
  {
     ...code here is like unrolled loop comb logic...'happens twice'
     ... is actually two sequential clock cycles in faster clock domain
     ... this infers registers then?
     ... during one clock of current my_func domain...
  }

  // Default everywhere is RATE=1
  some code happening per clock
}

Sequential ordering of the {...} blocks determines comb logic between the domains?

All very quickly sketched out