A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
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Reconsider assumption that all 2:1 muxes will have same path delay #134
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JulianKemmerer opened 2 years ago
Relating to https://github.com/JulianKemmerer/PipelineC/issues/133 where muxes are synthesized for different data width