User generated clock wires top level connections are not recognized by all timing tools

[JulianKemmerer]

TL/DR signals for user generated clocks with top level names, ex. clk_60p0hz, don't show up in constraint get_nets for all tools.

Ex. Graphics work uses CLK_MHZ pragma to mark a global wire as a generated clock of user defined freq (ex. slow 60FPS/Hz) clock in fabric...

Quartus would not create_clock for any of the top level names for get_ports/nets clk_60p0hz,clk_60p0hz_out

Vivado works with get_nets and the internal clock name ex. clk_60p0hz.

Double checked all the syn_keep,keep, and dont_touch attrs dont help...

But would create_clock from the full name of down to the register where the global wire frame clock 60Hz wire was being driven from: get_nets pixel_logic_33CLK_dac3dff5:pixel_logic_33CLK_dac3dff5|frame_clock_logic_0CLK_fc74e538:frame_clock_logic_pipelinec_app_c_l193_c3_d81c|frame_clock_reg[0]

[JulianKemmerer]

Small example

#include "compiler.h"
#include "uintN_t.h"
// Vivado works:
//#pragma PART "xc7a35ticsg324-1l" 
// Quartus does not: "clk_25p0 could not be matched with a net"
#pragma PART "5CEBA4F23C8"

// Make clock look like its user generated internally
// so that, regardless of frequency, the name is always the same
#define TEST_MHZ 25.0
uint1_t the_clock;
CLK_MHZ(the_clock, TEST_MHZ)
// Connect constant name top level port to internal the_clock
MAIN_MHZ(test, TEST_MHZ) 
#pragma FUNC_WIRES test
void test(uint1_t clock)
{
  the_clock = clock;
}
MAIN_MHZ(main, TEST_MHZ)
uint32_t main(uint32_t x, uint32_t y){
  return x + y;
}

[JulianKemmerer]

Only the dumb auto generated clock input register using itself as clock is seen as the source of the clock :roll_eyes: Node: pixel_0CLK_de264c78_clock_input_reg[0] was determined to be a clock but was found without an associated clock assignment