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JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
https://github.com/JulianKemmerer/PipelineC/wiki
GNU General Public License v3.0
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Raw VHDL interface should be bits per stage not slices #147

Closed JulianKemmerer closed 2 weeks ago

JulianKemmerer commented 2 years ago

Currently for basic things like adders ex. 32 bits is divided by the slices specified [0.5] = slice into two pieces = two 16b stages

First this is annoying because [0.499] is the same slicing (etc w/ close FP values) but still gets a different file, file name etc, blegh

Also its important to know how many bits per stage as being used. As in https://github.com/JulianKemmerer/PipelineC/issues/46 and https://github.com/JulianKemmerer/PipelineC/issues/48 and https://github.com/JulianKemmerer/PipelineC/issues/45 we want to know what hardware is produced by the synthesis tool - some bits per stage implement better than others, etc.

JulianKemmerer commented 2 years ago

Thanks @suarezvictor prompting this into an issue