celing rounding in coarse slicing

[suarezvictor]

It seems it can never met timing by floor rounding, see example log (it should start at 11)

pixel_logic Path delay: 271.003 ns (3.690 MHz)
Function: pixel_logic Target MHz: 40.0
pixel_logic : sliced coarsely ~= 10 clocks latency...

[JulianKemmerer]

271.003 ns split into 25ns (40MHz) chunks == 10.84012 chunks Rounded up to 11.

So there should be 11 stages = 10 clocks (1 stage == comb logic == 0 clocks)

[JulianKemmerer]

For now I dont think this is an issue

It doesnt seem like designs have been off by one when trying to meet timing - still needs iteration and ends up being more than 1 clock added anyway - so again dont think is a big issue or issue at all

[suarezvictor]

The aim of this is to not to lose the first try since I never see it meeting the timings

[JulianKemmerer]

I am saying the first try rarely ever meets timing

And it doesnt meet timing at +1 stages - it typically needs to almost double the number of stages (i.e. initial guess isnt that accurate)

(and so +- 1 rounding stuff isnt the root issue of not meeting timing)

[suarezvictor]

Understood, thanks