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JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
https://github.com/JulianKemmerer/PipelineC/wiki
GNU General Public License v3.0
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Upgrade sim to generate clocks in HDL #174

Open JulianKemmerer opened 1 year ago

JulianKemmerer commented 1 year ago

This also makes it easier to support multiple clocks

For Verilator first probably...IIUC this needs newer Verilator than have worked with before

Generate a generic testbench module with clock gen processes that instantiates the top when --sim ?