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JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
https://github.com/JulianKemmerer/PipelineC/wiki
GNU General Public License v3.0
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DDR AXI RAM shared resource bus control demo is broken #177

Closed JulianKemmerer closed 11 months ago

JulianKemmerer commented 1 year ago

Suspicious of recent shared resource bus arb changes regarding write req and data in same cycle...

Go back to simple graphics demo with DDR and debug?

https://github.com/JulianKemmerer/PipelineC/blob/47e5320f47dbb927fd92af160ef2e9f72d738ca8/examples/shared_resource_bus/axi_ddr/axi_xil_mem.c#L37

In the bus arb or the AXI port controller connection?

JulianKemmerer commented 11 months ago

This was resolved and was indeed having to do with mixed up order of write addr and data...