Open JulianKemmerer opened 2 years ago
This could be literally implemented with VHDL generics somehow but it doesn't need to be an exact copy of the functionality
Hello, I like using parameters in my IP's. It is possible to type function like: fun(ap_bit<8> a, ap_bit<8> b){} where "8" is a IP core parameter that could be changed, for example in Vivado block design?
Hey there @bartokon - something like you suggest is exactly what I want - but is not quite clear how to get there yet.
Maybe its faking it by sending C++ code with templates and stuff ex. ap_bit<8>
style through LLVM -> spit out a bunch of generated C code without template types.
Interesting to mention wanting to change something like a bit width - in a block diagram for example. Pipelining wise, the PipelineC tool produces hardware to meet timing for a specific known/fixed bit width/i.e some fixed logic - if that width changes the design may no longer meet timing :-/ Would need to run the PipelineC tool again it seems hmmm
Seed from my todo list:
Basic versions of this can be done with preprocessor but probably want something better
suarezvictor mentioned used C++ with LLVM to generate C code perhaps :+1: