FPGA Fault Injection Tutorial

This repository

This repository contains a guide to injecting errors on systems in FPGAs. This is a case study to explain the process described in the article “Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology”. The device under test selected for this demo is a finite impulse response (FIR) filter, but this methodology can be applied to other modules in the same way.

Files

• The modules of the experimental set-up and UART can be found in the DUT HDL sources folder.
• The SEM IP files are in the SEM IP source files folder.
• The Fault Injection Emulation Process on a FIR Filter file is the step-by-step guide.

Tools and harware

• Vivado Design Suite
• Nexys 4 DDR board based on the latest Artix-7™ FPGA from Xilinx.
• Automatic configuration memory error-injection (ACME) tool.

License

This project is licensed under GPLv3 - see the LICENSE file for details.