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test-neorv32
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sonar scanner crash
#71
LeFl0w
closed
1 year ago
1
Test 2 coverages
#70
LeFl0w
closed
1 year ago
0
false positive
#69
LeFl0w
opened
1 year ago
2
Find reset signals and their usagevhdl:VHDL1024
#68
LeFl0w
closed
1 year ago
2
vhdl:VHDL1000 All input ports of an entity should be connected
#67
LeFl0w
closed
1 year ago
2
github action fail
#66
LeFl0w
opened
1 year ago
1
update main workflow
#65
LeFl0w
closed
1 year ago
0
metric mesure resultat curieux
#64
LeFl0w
closed
1 year ago
7
remove vunit dirty patch
#63
LeFl0w
closed
1 year ago
1
annotation sonarqube activity
#62
LeFl0w
closed
1 year ago
1
Yosys Metrics
#61
racodond
closed
1 year ago
5
Test cicd
#60
LeFl0w
closed
1 year ago
0
submodule strategy
#59
LeFl0w
closed
1 year ago
0
add neorv32 patch to CI/CD
#58
LeFl0w
closed
1 year ago
0
broken pipeline
#57
LeFl0w
closed
1 year ago
6
github workflow update
#56
LeFl0w
closed
1 year ago
1
nouvelle "règle"
#55
LeFl0w
closed
1 year ago
0
plugin metrics
#54
LeFl0w
closed
1 year ago
4
VHDL1041 This flip-flop defines a complex enable (enable involving several signals).
#53
LeFl0w
closed
1 year ago
3
nouvelle règle : détection process multiples
#52
LeFl0w
opened
1 year ago
0
VHDL214 Generate statements should be identified by labels
#51
LeFl0w
closed
1 year ago
1
VHDL1046 Enable signals should not be reused in non-enable way
#50
LeFl0w
closed
1 year ago
1
VHDL206 Functions and procedures should not be used in design
#49
LeFl0w
closed
1 year ago
1
VHDL1000 All input ports of an entity should be connected
#48
LeFl0w
closed
1 year ago
1
affichage colorisation syntaxique
#47
LeFl0w
opened
1 year ago
1
recherche signal
#46
LeFl0w
closed
1 year ago
2
Signals from a process' sensitivity list should not be affected in this process
#45
LeFl0w
closed
1 year ago
0
VHDL1702 : Conditional branching statements ("if", "case", "while" and "for" loops) should not be too deeply nested
#44
LeFl0w
opened
1 year ago
3
FSM implementations should be manually reviewed
#43
LeFl0w
closed
1 year ago
1
File name should comply with a naming convention
#42
LeFl0w
closed
1 year ago
3
File header should match a template
#41
LeFl0w
closed
1 year ago
4
All output ports (and optionally all input ports) of a component should be mapped
#40
LeFl0w
opened
1 year ago
1
CI/CD
#39
LeFl0w
closed
1 year ago
4
New rule: Libraries should be written with the same case
#38
racodond
closed
1 year ago
1
Support clock signal as record
#37
racodond
opened
1 year ago
0
Add details when reset is used as enable and vice-versa
#36
racodond
opened
1 year ago
0
RULE Reset signal names should comply with a naming convention
#35
racodond
closed
1 year ago
1
RULE Only authorized libraries should be used
#34
racodond
closed
1 year ago
2
Enable
#33
racodond
closed
1 year ago
0
Enable : nouvelle règle
#32
racodond
closed
1 year ago
1
RULE Find enable signals and their usage
#31
racodond
closed
1 year ago
1
RULE Entity ports should be commented
#30
racodond
closed
1 year ago
1
RULE Vector reset assignments should not be hardcoded
#29
racodond
opened
1 year ago
1
RULE End block identifier should be repeated at the end
#28
racodond
closed
1 year ago
1
RULE All declared elements should be used in their corresponding scope
#27
racodond
opened
1 year ago
1
RULEOutput signals should not be constant
#26
racodond
closed
1 year ago
1
RULE All output signals of low-level entities should be registered
#25
racodond
opened
1 year ago
4
Nouvelle règle initialisation de vecteur avec un L H : tri state valeur non faissable interne
#24
racodond
closed
1 year ago
1
RULE All input ports of an entity should be connected
#23
racodond
closed
1 year ago
1
All reserved words should have the same case
#22
racodond
closed
1 year ago
2
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