Failed in test_loragw_reg test, anyone can help?

[rossihwang]

My hardware are ic880a and raspberry pi, They are connected through SPI. I modify the lastest code a little(add the reset pin control). I tested the SPI write function with the logic analysor, it works well. But it can't pass the test_loragw_reg test, in which some read back values are fault.

Beginning of test for loragw_reg.c
Note: SPI port opened and configured ok
Note: Reset pin toggle ok
Note: SPI read success
INFO: no FPGA detected
Note: SPI read success
Note: SPI write success
Note: success connecting the concentrator
Note: SPI write success
Start of register verification
Note: SPI read success
###MISMATCH### reg number 0 read: 2 (2) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 1 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 2 read: 187 (bb) default: 103 (67)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 3 read: 45404 (b15c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 4 read: 32 (20) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 5 read: 163 (a3) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 6 read: 126 (7e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 7 read: 169 (a9) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 8 read: 176 (b0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 9 read: 164 (a4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 10 read: 115 (73) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 11 read: 83 (53) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 12 read: 6084 (17c4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 13 read: 127 (7f) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 14 read: 66 (42) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 15 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 16 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 17 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 18 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 19 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 20 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 21 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 22 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 23 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 24 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 25 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 26 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 27 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 28 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 29 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 30 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 31 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 32 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 33 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 34 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 35 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 36 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 37 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 38 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 39 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 40 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 41 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 42 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 43 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 44 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 45 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 46 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 47 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 48 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 49 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 50 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 51 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 52 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 53 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 54 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 55 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 56 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 57 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 58 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 59 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 60 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 61 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 62 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 63 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 64 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 65 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 66 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 67 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 68 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 69 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 70 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 71 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 72 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 73 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 74 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 75 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 76 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 77 read: 3 (3) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 78 read: 11 (b) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 79 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 80 read: 70 (46) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 81 read: 32 (20) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 82 read: 213 (d5) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 83 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 84 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 85 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 86 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 87 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 88 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 89 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 90 read: 5 (5) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 91 read: 50 (32) default: 240 (f0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 92 read: 747 (2eb) default: -384 (fffffe80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 93 read: 1320 (528) default: -128 (ffffff80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 94 read: -2395 (fffff6a5) default: 128 (80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 95 read: 622 (26e) default: 384 (180)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 96 read: -958 (fffffc42) default: -384 (fffffe80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 97 read: 304 (130) default: -128 (ffffff80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 98 read: 3313 (cf1) default: 128 (80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 99 read: -503 (fffffe09) default: 384 (180)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 100 read: 3207 (c87) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 101 read: -1634 (fffff99e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 102 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 103 read: 4 (4) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 104 read: 44 (2c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 105 read: 55 (37) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 106 read: 44 (2c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 107 read: 125 (7d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 108 read: 49 (31) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 109 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 110 read: 18 (12) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 111 read: 121 (79) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 112 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 113 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 114 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 115 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 116 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 117 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 118 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 119 read: 6 (6) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 120 read: 13 (d) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 121 read: 10 (a) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 122 read: 6 (6) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 123 read: 0 (0) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 124 read: 14 (e) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 125 read: 11 (b) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 126 read: 0 (0) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 127 read: 2 (2) default: 5 (5)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 128 read: 21184 (52c0) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 129 read: 49752 (c258) default: 4092 (ffc)
Note: SPI read success
###MISMATCH### reg number 130 read: 224 (e0) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 131 read: 211 (d3) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 132 read: 64 (40) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 133 read: 9 (9) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 134 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 135 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 136 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 137 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 138 read: 186 (ba) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 139 read: 78 (4e) default: 29 (1d)
Note: SPI read success
###MISMATCH### reg number 140 read: 3 (3) default: 9 (9)
Note: SPI read success
###MISMATCH### reg number 141 read: 3 (3) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 142 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 143 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 144 read: 10 (a) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 145 read: 6 (6) default: 2 (2)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 146 read: 55823 (da0f) default: 10 (a)
Note: SPI read success
###MISMATCH### reg number 147 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 148 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 149 read: 5 (5) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 150 read: 1 (1) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 151 read: 100 (64) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 152 read: 61 (3d) default: 255 (ff)
Note: SPI read success
###MISMATCH### reg number 153 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 154 read: 118 (76) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 155 read: 9 (9) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 156 read: 10 (a) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 157 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 158 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 159 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 160 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 161 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 162 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 163 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 164 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 165 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 166 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 167 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 168 read: 142 (8e) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 169 read: 251 (fb) default: 32 (20)
Note: SPI read success
###MISMATCH### reg number 170 read: 141 (8d) default: 100 (64)
Note: SPI read success
###MISMATCH### reg number 171 read: 42 (2a) default: 100 (64)
Note: SPI read success
###MISMATCH### reg number 172 read: 3 (3) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 173 read: 11 (b) default: 5 (5)
Note: SPI read success
###MISMATCH### reg number 174 read: 10 (a) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 175 read: 53 (35) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 176 read: 46 (2e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 177 read: 32 (20) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 178 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 179 read: 50 (32) default: 0 (0)
Note: SPI write success
Note: SPI read success
+++MATCH+++ reg number 180 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 181 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 182 read: 0 (0) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 183 read: 12407 (3077) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 184 read: 9 (9) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 185 read: 0 (0) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 186 read: 7 (7) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 187 read: 88 (58) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 188 read: 100 (64) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 189 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 190 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 191 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 192 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 193 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 194 read: 1 (1) default: 5 (5)
Note: SPI read success
###MISMATCH### reg number 195 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 196 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 197 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 198 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 199 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 200 read: 178 (b2) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 201 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 202 read: 5 (5) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 203 read: 10 (a) default: 2 (2)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 204 read: 6370 (18e2) default: 10 (a)
Note: SPI read success
+++MATCH+++ reg number 205 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 206 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 207 read: 26 (1a) default: 10 (a)
Note: SPI read success
###MISMATCH### reg number 208 read: 2 (2) default: 3 (3)
Note: SPI read success
###MISMATCH### reg number 209 read: 115 (73) default: 29 (1d)
Note: SPI read success
###MISMATCH### reg number 210 read: 16 (10) default: 36 (24)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 211 read: 10774 (2a16) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 212 read: 0 (0) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 213 read: 2 (2) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 214 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 215 read: 47 (2f) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 216 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 217 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 218 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 219 read: 15 (f) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 220 read: 2 (2) default: 3 (3)
Note: SPI read success
+++MATCH+++ reg number 221 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 222 read: 5 (5) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 223 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 224 read: 16 (10) default: 255 (ff)
Note: SPI read success
###MISMATCH### reg number 225 read: 97 (61) default: 128 (80)
Note: SPI read success
###MISMATCH### reg number 226 read: 5 (5) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 227 read: 3 (3) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 228 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 229 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 230 read: 3 (3) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 231 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 232 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 233 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 234 read: 16 (10) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 235 read: 1 (1) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 236 read: 4384 (1120) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 4 # chunk 4 # transferred 4 
Note: SPI burst read success
###MISMATCH### reg number 237 read: 2253873348 (865760c4) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 4 # chunk 4 # transferred 4 
Note: SPI burst read success
###MISMATCH### reg number 238 read: 3794790410 (e22fe80a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 239 read: 31 (1f) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 240 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 241 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 242 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 243 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 244 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 245 read: 37 (25) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 246 read: 228 (e4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 247 read: 0 (0) default: 1 (1)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 248 read: 14796 (39cc) default: 0 (0)
Note: SPI write success
Note: SPI read success
###MISMATCH### reg number 249 read: 40 (28) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 250 read: 126 (7e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 251 read: 89 (59) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 252 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 253 read: 37 (25) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 254 read: 212 (d4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 255 read: 192 (c0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 256 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 257 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 258 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 259 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 260 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 261 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 262 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 263 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 264 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 265 read: 15 (f) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 266 read: 9 (9) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 267 read: 4 (4) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 268 read: 8 (8) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 269 read: 28 (1c) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 270 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 271 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 272 read: 0 (0) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 273 read: 40994 (a022) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 274 read: 137 (89) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 275 read: 148 (94) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 276 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 277 read: 160 (a0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 278 read: 12 (c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 279 read: 34 (22) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 280 read: 187 (bb) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 281 read: 115 (73) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 282 read: 98 (62) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 283 read: 209 (d1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 284 read: 141 (8d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 285 read: 8 (8) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 286 read: 22 (16) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 287 read: 1332 (534) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 288 read: 39121 (98d1) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 4 # chunk 4 # transferred 4 
Note: SPI burst read success
###MISMATCH### reg number 289 read: 2241045333 (8593a355) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 290 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 291 read: 12 (c) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 292 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 293 read: 13 (d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 294 read: 5 (5) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 295 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 296 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 297 read: 13 (d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 298 read: 3 (3) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 299 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 300 read: 5 (5) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 301 read: 208 (d0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 302 read: 199 (c7) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 303 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 304 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 305 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 306 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 307 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 308 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 309 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 310 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 311 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 312 read: 97 (61) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 313 read: 108 (6c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 314 read: 44 (2c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 315 read: 56 (38) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 316 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 317 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 318 read: -32 (ffffffe0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 319 read: 24 (18) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 320 read: 4715 (126b) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 321 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 322 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 323 read: 12 (c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 324 read: 24 (18) default: 0 (0)
Note: SPI write success
Note: SPI read success
###MISMATCH### reg number 325 read: 72 (48) default: 0 (0)
End of register verification
Note: SPI write success
Note: SPI write success
Note: SPI read success
IMPLICIT_PAYLOAD_LENGHT = 144 (should be 197)
Note: SPI read success
Note: SPI write success
Note: SPI read success
FRAME_SYNCH_PEAK2_POS = 2 (should be 11)
lgw_spi_wb:321: BURST WRITE: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
PREAMBLE_SYMB1_NB = 33272 (should be 49253)
lgw_spi_wb:321: BURST WRITE: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 4410 (should be 3173)
lgw_spi_wb:321: BURST WRITE: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
IF_FREQ_1 = -1782 (should be -1947)
lgw_spi_wb:321: BURST WRITE: to trans 256 # chunk 256 # transferred 256 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 256 # chunk 256 # transferred 256 
Note: SPI burst read success
Note: SPI port closed
Note: success disconnecting the concentrator
End of test for loragw_reg.c

Aslo I can ensure that the interface is connected well,

thanks!

[bitmorse]

I'm trying to get the same test to work and have the same hardware. I'm stuck with the ic880a not responding. Could you please share how you got the reset to work?

[rossihwang]

hi @bitmorse . I use the wiringPi library to do so, though it is not a pretty way, because you need root to run the application.

first, you should install wiringPi. then add some code at the end of the lgw_spi_open() in loragw_spi.native.c

#include <wiringPi.h>

int lgw_spi_open() {

    ...

    wiringPiSetup();
    pinMode(31, OUTPUT); // You can use other pin
    digitalWrite(31, HIGH);
    // Maybe need some delay here. Delay need to be more than 100ns.
    digitalWrite(31, LOW);
    DEBUG_MSG("Note: Reset pin toggle ok\n");

    return LGW_SPI_SUCCESS;
}

remember to add -lwiringPi to you LIBS in Makefile.

That is it!

[bitmorse]

Thank you very much! Which hardware reset pin did you connect to on the iC880a though? There seem to be 2.

On Mon, 7 Dec 2015 at 06:28, Rossi Hwang notifications@github.com wrote:

hi @bitmorse https://github.com/bitmorse . I use the wiringPi library to do so, though it is not a pretty way, because you need root to run the application.

first, you should install wiringPi. then add some code at the end of the lgw_spi_open() in loragw_spi.native.c

include

int lgw_spi_open() {

...

wiringPiSetup();
pinMode(31, OUTPUT); // You can use other pin
digitalWrite(31, HIGH);
// Maybe need some delay here. Delay need to be more than 100ns.
digitalWrite(31, LOW);
DEBUG_MSG("Note: Reset pin toggle ok\n");

return LGW_SPI_SUCCESS;

}

remember to add -lwiringPi to you LIBS in Makefile.

That is it!

— Reply to this email directly or view it on GitHub https://github.com/Lora-net/lora_gateway/issues/10#issuecomment-162415463 .

[bitmorse]

@rossihwang after setting k.cs_change=0 everywhere and then trying the pkt_logger, everything works fine. we can also verify that setting the SPI reset pin first is necessary for things to work.

[rossihwang]

@bitmorse Really?! I would have a try! Actually I do the reset because the IMST engineerer told me that. BTW, Do you modify the PCB according to the file "iC880A_AN014_USB_modifications_for_SPI_V1_2.pdf"??

[rossihwang]

@bitmorse I tried it, the "test_loragw_reg" works better but still some error!

Beginning of test for loragw_reg.c
Start of register verification
+++MATCH+++ reg number 0 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 1 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 2 read: 103 (67) default: 103 (67)
+++MATCH+++ reg number 3 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 4 read: 146 (92) default: 0 (0)
+++MATCH+++ reg number 5 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 6 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 7 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 8 read: 125 (7d) default: 0 (0)
+++MATCH+++ reg number 9 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 10 read: 8 (8) default: 0 (0)
+++MATCH+++ reg number 11 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 12 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 13 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 14 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 15 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 16 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 17 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 18 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 19 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 20 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 21 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 22 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 23 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 24 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 25 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 26 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 27 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 28 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 29 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 30 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 31 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 32 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 33 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 34 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 35 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 36 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 37 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 38 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 39 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 40 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 41 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 42 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 43 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 44 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 45 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 46 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 47 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 48 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 49 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 50 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 51 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 52 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 53 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 54 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 55 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 56 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 57 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 58 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 59 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 60 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 61 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 62 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 63 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 64 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 65 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 66 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 67 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 68 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 69 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 70 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 71 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 72 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 73 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 74 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 75 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 76 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 77 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 78 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 79 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 80 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 81 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 82 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 83 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 84 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 85 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 86 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 87 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 88 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 89 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 90 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 91 read: 240 (f0) default: 240 (f0)
+++MATCH+++ reg number 92 read: -384 (fffffe80) default: -384 (fffffe80)
###MISMATCH### reg number 93 read: 31 (1f) default: -128 (ffffff80)
###MISMATCH### reg number 94 read: 384 (180) default: 128 (80)
###MISMATCH### reg number 95 read: 30 (1e) default: 384 (180)
###MISMATCH### reg number 96 read: 128 (80) default: -384 (fffffe80)
###MISMATCH### reg number 97 read: 1 (1) default: -128 (ffffff80)
###MISMATCH### reg number 98 read: 0 (0) default: 128 (80)
###MISMATCH### reg number 99 read: 0 (0) default: 384 (180)
+++MATCH+++ reg number 100 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 101 read: 3584 (e00) default: 0 (0)
+++MATCH+++ reg number 102 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 103 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 104 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 105 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 106 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 107 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 108 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 109 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 110 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 111 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 112 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 113 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 114 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 115 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 116 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 117 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 118 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 119 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 120 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 121 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 122 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 123 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 124 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 125 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 126 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 127 read: 5 (5) default: 5 (5)
+++MATCH+++ reg number 128 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 129 read: 1807 (70f) default: 4092 (ffc)
###MISMATCH### reg number 130 read: 0 (0) default: 7 (7)
+++MATCH+++ reg number 131 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 132 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 133 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 134 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 135 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 136 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 137 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 138 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 139 read: 29 (1d) default: 29 (1d)
+++MATCH+++ reg number 140 read: 9 (9) default: 9 (9)
+++MATCH+++ reg number 141 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 142 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 143 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 144 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 145 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 146 read: 10 (a) default: 10 (a)
###MISMATCH### reg number 147 read: 0 (0) default: 1 (1)
+++MATCH+++ reg number 148 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 149 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 150 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 151 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 152 read: 255 (ff) default: 255 (ff)
+++MATCH+++ reg number 153 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 154 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 155 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 156 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 157 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 158 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 159 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 160 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 161 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 162 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 163 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 164 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 165 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 166 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 167 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 168 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 169 read: 32 (20) default: 32 (20)
+++MATCH+++ reg number 170 read: 100 (64) default: 100 (64)
+++MATCH+++ reg number 171 read: 100 (64) default: 100 (64)
+++MATCH+++ reg number 172 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 173 read: 5 (5) default: 5 (5)
+++MATCH+++ reg number 174 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 175 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 176 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 177 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 178 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 179 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 180 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 181 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 182 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 183 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 184 read: 0 (0) default: 1 (1)
+++MATCH+++ reg number 185 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 186 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 187 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 188 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 189 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 190 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 191 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 192 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 193 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 194 read: 5 (5) default: 5 (5)
+++MATCH+++ reg number 195 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 196 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 197 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 198 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 199 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 200 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 201 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 202 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 203 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 204 read: 10 (a) default: 10 (a)
###MISMATCH### reg number 205 read: 0 (0) default: 1 (1)
+++MATCH+++ reg number 206 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 207 read: 10 (a) default: 10 (a)
+++MATCH+++ reg number 208 read: 3 (3) default: 3 (3)
+++MATCH+++ reg number 209 read: 29 (1d) default: 29 (1d)
+++MATCH+++ reg number 210 read: 36 (24) default: 36 (24)
+++MATCH+++ reg number 211 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 212 read: 0 (0) default: 2 (2)
+++MATCH+++ reg number 213 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 214 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 215 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 216 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 217 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 218 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 219 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 220 read: 3 (3) default: 3 (3)
+++MATCH+++ reg number 221 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 222 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 223 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 224 read: 255 (ff) default: 255 (ff)
+++MATCH+++ reg number 225 read: 128 (80) default: 128 (80)
+++MATCH+++ reg number 226 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 227 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 228 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 229 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 230 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 231 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 232 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 233 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 234 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 235 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 236 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 237 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 238 read: 150994944 (9000000) default: 0 (0)
+++MATCH+++ reg number 239 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 240 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 241 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 242 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 243 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 244 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 245 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 246 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 247 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 248 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 249 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 250 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 251 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 252 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 253 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 254 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 255 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 256 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 257 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 258 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 259 read: 0 (0) default: 1 (1)
+++MATCH+++ reg number 260 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 261 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 262 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 263 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 264 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 265 read: 1 (1) default: 2 (2)
###MISMATCH### reg number 266 read: 0 (0) default: 4 (4)
###MISMATCH### reg number 267 read: 1 (1) default: 2 (2)
###MISMATCH### reg number 268 read: 2 (2) default: 4 (4)
###MISMATCH### reg number 269 read: 10 (a) default: 0 (0)
+++MATCH+++ reg number 270 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 271 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 272 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 273 read: 768 (300) default: 0 (0)
###MISMATCH### reg number 274 read: 3 (3) default: 0 (0)
###MISMATCH### reg number 275 read: 29 (1d) default: 0 (0)
+++MATCH+++ reg number 276 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 277 read: 6 (6) default: 0 (0)
+++MATCH+++ reg number 278 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 279 read: 8 (8) default: 0 (0)
###MISMATCH### reg number 280 read: 56 (38) default: 0 (0)
###MISMATCH### reg number 281 read: 23 (17) default: 0 (0)
###MISMATCH### reg number 282 read: 255 (ff) default: 0 (0)
###MISMATCH### reg number 283 read: 128 (80) default: 0 (0)
+++MATCH+++ reg number 284 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 285 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 286 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 287 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 288 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 289 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 290 read: 9 (9) default: 0 (0)
+++MATCH+++ reg number 291 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 292 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 293 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 294 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 295 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 296 read: 9 (9) default: 0 (0)
+++MATCH+++ reg number 297 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 298 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 299 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 300 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 301 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 302 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 303 read: 1 (1) default: 0 (0)
+++MATCH+++ reg number 304 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 305 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 306 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 307 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 308 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 309 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 310 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 311 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 312 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 313 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 314 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 315 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 316 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 317 read: 0 (0) default: 1 (1)
+++MATCH+++ reg number 318 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 319 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 320 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 321 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 322 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 323 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 324 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 325 read: 0 (0) default: 0 (0)
End of register verification
IMPLICIT_PAYLOAD_LENGHT = 197 (should be 197)
FRAME_SYNCH_PEAK2_POS = 11 (should be 11)
PREAMBLE_SYMB1_NB = 0 (should be 49253)
ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 0 (should be 3173)
IF_FREQ_1 = 0 (should be -1947)
End of test for loragw_reg.c

Would you tell me how do you connect the RPi with the ic880A?

[bitmorse]

did you make sure the board resets prior to spi comms? and did you set cs_change to 0 in every occurrence (4 times) ? are you using spidev0.1 on raspi? are you using the latest lora-gateway version?

we only connected spi lines and ground. we do not use usb to power the ic880a. we reset "manually" at the moment.

[rossihwang]

Think you so much. I found I didn't modify all the cs_change to 0. It works now!

[abouillot]

I'm ending up in a similar situation. I'm using latest raspbian Jessie on a Rapberry Pi B+ board

No LSB modules are available.
Distributor ID: Raspbian
Description:    Raspbian GNU/Linux 8.0 (jessie)
Release:        8.0
Codename:       jessie

Linux raspberrypi 4.1.13+ #826 PREEMPT Fri Nov 13 20:13:22 GMT 2015 armv6l GNU/Linux

I've cloned the lora_gateway repositiry, changed the 4 occurrences of cs_change to 0:

pi@raspberrrypi:~/lora_gateway/libloragw $ grep -r cs_ *
src/loragw_spi.native.c:        k.cs_change = 0;
src/loragw_spi.native.c:        k.cs_change = 0;
src/loragw_spi.native.c:        k[0].cs_change = 0;
src/loragw_spi.native.c:        k[1].cs_change = 0;
src/loragw_spi.native.c:        k[0].cs_change = 0;
src/loragw_spi.native.c:        k[1].cs_change = 0;

I'm using spidev0.0, the board is reset using GPIO0 pin 11 and the outcome is similar to last @rossihwang output:

pi@raspberrrypi:~/lora_gateway/libloragw $ sudo ./test_loragw_reg
Beginning of test for loragw_reg.c
Start of register verification
+++MATCH+++ reg number 0 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 1 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 2 read: 103 (67) default: 103 (67)
+++MATCH+++ reg number 3 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 4 read: 217 (d9) default: 0 (0)
+++MATCH+++ reg number 5 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 6 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 7 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 8 read: 244 (f4) default: 0 (0)
+++MATCH+++ reg number 9 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 10 read: 138 (8a) default: 0 (0)
+++MATCH+++ reg number 11 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 12 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 13 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 14 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 15 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 16 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 17 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 18 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 19 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 20 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 21 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 22 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 23 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 24 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 25 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 26 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 27 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 28 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 29 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 30 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 31 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 32 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 33 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 34 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 35 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 36 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 37 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 38 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 39 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 40 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 41 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 42 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 43 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 44 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 45 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 46 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 47 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 48 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 49 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 50 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 51 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 52 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 53 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 54 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 55 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 56 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 57 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 58 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 59 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 60 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 61 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 62 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 63 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 64 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 65 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 66 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 67 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 68 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 69 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 70 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 71 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 72 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 73 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 74 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 75 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 76 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 77 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 78 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 79 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 80 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 81 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 82 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 83 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 84 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 85 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 86 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 87 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 88 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 89 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 90 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 91 read: 240 (f0) default: 240 (f0)
+++MATCH+++ reg number 92 read: -384 (fffffe80) default: -384 (fffffe80)
+++MATCH+++ reg number 93 read: -128 (ffffff80) default: -128 (ffffff80)
+++MATCH+++ reg number 94 read: 128 (80) default: 128 (80)
+++MATCH+++ reg number 95 read: 384 (180) default: 384 (180)
+++MATCH+++ reg number 96 read: -384 (fffffe80) default: -384 (fffffe80)
+++MATCH+++ reg number 97 read: -128 (ffffff80) default: -128 (ffffff80)
+++MATCH+++ reg number 98 read: 128 (80) default: 128 (80)
+++MATCH+++ reg number 99 read: 384 (180) default: 384 (180)
+++MATCH+++ reg number 100 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 101 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 102 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 103 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 104 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 105 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 106 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 107 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 108 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 109 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 110 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 111 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 112 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 113 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 114 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 115 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 116 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 117 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 118 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 119 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 120 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 121 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 122 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 123 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 124 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 125 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 126 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 127 read: 5 (5) default: 5 (5)
+++MATCH+++ reg number 128 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 129 read: 4092 (ffc) default: 4092 (ffc)
+++MATCH+++ reg number 130 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 131 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 132 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 133 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 134 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 135 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 136 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 137 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 138 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 139 read: 29 (1d) default: 29 (1d)
+++MATCH+++ reg number 140 read: 9 (9) default: 9 (9)
+++MATCH+++ reg number 141 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 142 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 143 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 144 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 145 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 146 read: 10 (a) default: 10 (a)
+++MATCH+++ reg number 147 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 148 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 149 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 150 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 151 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 152 read: 255 (ff) default: 255 (ff)
+++MATCH+++ reg number 153 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 154 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 155 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 156 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 157 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 158 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 159 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 160 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 161 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 162 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 163 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 164 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 165 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 166 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 167 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 168 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 169 read: 32 (20) default: 32 (20)
+++MATCH+++ reg number 170 read: 100 (64) default: 100 (64)
+++MATCH+++ reg number 171 read: 100 (64) default: 100 (64)
+++MATCH+++ reg number 172 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 173 read: 5 (5) default: 5 (5)
+++MATCH+++ reg number 174 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 175 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 176 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 177 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 178 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 179 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 180 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 181 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 182 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 183 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 184 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 185 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 186 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 187 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 188 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 189 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 190 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 191 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 192 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 193 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 194 read: 5 (5) default: 5 (5)
+++MATCH+++ reg number 195 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 196 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 197 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 198 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 199 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 200 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 201 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 202 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 203 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 204 read: 10 (a) default: 10 (a)
+++MATCH+++ reg number 205 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 206 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 207 read: 10 (a) default: 10 (a)
+++MATCH+++ reg number 208 read: 3 (3) default: 3 (3)
+++MATCH+++ reg number 209 read: 29 (1d) default: 29 (1d)
+++MATCH+++ reg number 210 read: 36 (24) default: 36 (24)
+++MATCH+++ reg number 211 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 212 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 213 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 214 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 215 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 216 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 217 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 218 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 219 read: 8 (8) default: 8 (8)
+++MATCH+++ reg number 220 read: 3 (3) default: 3 (3)
+++MATCH+++ reg number 221 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 222 read: 7 (7) default: 7 (7)
+++MATCH+++ reg number 223 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 224 read: 255 (ff) default: 255 (ff)
+++MATCH+++ reg number 225 read: 128 (80) default: 128 (80)
+++MATCH+++ reg number 226 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 227 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 228 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 229 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 230 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 231 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 232 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 233 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 234 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 235 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 236 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 237 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 238 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 239 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 240 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 241 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 242 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 243 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 244 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 245 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 246 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 247 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 248 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 249 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 250 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 251 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 252 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 253 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 254 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 255 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 256 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 257 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 258 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 259 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 260 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 261 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 262 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 263 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 264 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 265 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 266 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 267 read: 2 (2) default: 2 (2)
+++MATCH+++ reg number 268 read: 4 (4) default: 4 (4)
+++MATCH+++ reg number 269 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 270 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 271 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 272 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 273 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 274 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 275 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 276 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 277 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 278 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 279 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 280 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 281 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 282 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 283 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 284 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 285 read: 238 (ee) default: 0 (0)
###MISMATCH### reg number 286 read: 66 (42) default: 0 (0)
+++MATCH+++ reg number 287 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 288 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 289 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 290 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 291 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 292 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 293 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 294 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 295 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 296 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 297 read: 0 (0) default: 0 (0)
###MISMATCH### reg number 298 read: 7 (7) default: 0 (0)
+++MATCH+++ reg number 299 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 300 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 301 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 302 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 303 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 304 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 305 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 306 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 307 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 308 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 309 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 310 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 311 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 312 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 313 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 314 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 315 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 316 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 317 read: 1 (1) default: 1 (1)
+++MATCH+++ reg number 318 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 319 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 320 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 321 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 322 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 323 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 324 read: 0 (0) default: 0 (0)
+++MATCH+++ reg number 325 read: 0 (0) default: 0 (0)
End of register verification
IMPLICIT_PAYLOAD_LENGHT = 197 (should be 197)
FRAME_SYNCH_PEAK2_POS = 11 (should be 11)
PREAMBLE_SYMB1_NB = 49253 (should be 49253)
ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 3173 (should be 3173)
IF_FREQ_1 = -1947 (should be -1947)
End of test for loragw_reg.c

I guess I forgot something, but ran out of idea.

[JiapengLi]

@abouillot which spi module did you use? spi-bcm2835 or spi-2708? Could check with lsmod.

[abouillot]

The module is bcm2835:

pi@raspberrypi:~ $ lsmod
Module                  Size  Used by
cfg80211              499834  0
rfkill                 22491  1 cfg80211
spi_bcm2835             7948  0
bcm2835_gpiomem         3703  0
snd_bcm2835            22317  3
snd_pcm                92581  1 snd_bcm2835
snd_timer              23454  1 snd_pcm
snd                    68161  9 snd_bcm2835,snd_timer,snd_pcm
uio_pdrv_genirq         3690  0
uio                    10002  1 uio_pdrv_genirq
i2c_dev                 6730  0
fuse                   91981  3
ipv6                  360374  24

[JiapengLi]

@abouillot From my experience lora_gateway works correctly with RPi driver bcm-2708 (older than bcm-2835), no patch needed. So i guess there is different cs_change implementation between bcm-2708 and bcm-2835.

I referred this article https://www.kernel.org/doc/htmldocs/device-drivers/API-struct-spi-transfer.html, although not very easy to understand. But It seems the cs_change signal is generally used to inactive chip select signal for standard implementation.

Not very sure, but I think your patch make sense. Thank your for the sharing!

[rossihwang]

@abouillot I also work on RPI B+, the spi is snd_bcm2835. The SPI test may not pass completly. I think you should try the ohter tests.

[sylvain-miermont]

@abouillot Hi It's ok for some registers to display a mismatch because some special registers have a value that is not always constant during initialization, but the test_loragw_reg program doesn't know if a register is special or not, and test them all sequentially.

Simply said, as soon as you get matching values on the latest section:

IMPLICIT_PAYLOAD_LENGHT = 197 (should be 197)
FRAME_SYNCH_PEAK2_POS = 11 (should be 11)
PREAMBLE_SYMB1_NB = 49253 (should be 49253)
ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 3173 (should be 3173)
IF_FREQ_1 = -1947 (should be -1947)

you can assume that the SX1301 is working as intended, and SPI communication is ok. The register-by-register test that is done initially was designed for internal development and debug, and neither the documentation, nor the program itself explains how the results should be interpreted. My apologies for that.

If you have any doubt about the SPI communication reliability, or start seeing a SX1301 act funny, please run the util_spi_stress for a couple of minutes or hours. Since Broadcom fixed their formerly barely functional drivers, if your wiring is done properly (ground wire close to SCK/MOSI/MISO wires, length kept reasonable) your SPI link should be rock-solid.

S.

[abouillot]

@sylvain-miermont Hi,

Thanks for the clarification. I have the GW functional for some days now, but was puzzled by this discrepancy in the test results. I'm reassured now assuming all is OK and will look elsewhere in case I face some issue.

[mcoracin]

Hi all,

concerning possible MISMATCH returned by the test_loragw_reg binary, it is expected for some registers. All the registers *_DATA correspond to some randomly initilialized memory, so may differ from one run to the other.

So if the MISMATCH you get are on those registers, don't worry, it is expected.

I close this issue.

[JiapengLi]

@mcoracin Hi Michael, Would you please check the usage of cs_change? I get several customers report that lora_gateway cs_change usage doesn't follow Linux standard.

[mcoracin]

@JiapengLi Hi, It is true that there is something unclear here. The lora_gateway was initially tested with various hosts, Raspberry Pi (spi_bcm2708), PCduino, Kerlink hosts (don't know what they have inside), and it is working with all of them the way is is released. More recently, we have seen several hosts behaving differently with the cs_change, like the RPi with spi_bcm2835 and few others, and for which reverting the cs_change to 0 fixed issues.

I could not spend time on this so far to analyze deeper the issue, and how it could be fixed for all platforms.

I'll try to check this when possible.

In the meantime, if anyone as a final answer on this, I'm open! :)

[mcoracin]

Hello,

For your information, the latest release v3.2.1 comes with the cs_change set to 0. This lets the SPI driver handle chip select.

It has been tested on Raspberry Pi with both spi_bcm2708 and spi_bcm2835 drivers, and it works with both.

Let me know if you face any issue with other SPI drivers.

Regards