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MIPT-ILab / mipt-mips

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
http://mipt-ilab.github.io/mipt-mips/
MIT License
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Add bset instruction. #1506

Closed panferovi closed 2 years ago

panferovi commented 2 years ago

Single-Bit Set (Register) instruction

Mnemonic: bset rd, rs1, rs2

Opcode : 1100110.

This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

Operation:

let index = X(rs2) & (XLEN - 1);
X(rd) = X(rs1) | (1 << index);
pavelkryukov commented 2 years ago

Please fix build + resolve merge conflicts.

codecov[bot] commented 2 years ago

Codecov Report

Merging #1506 (3f62543) into main (6387fcf) will increase coverage by 0.00%. The diff coverage is 100.00%.

Impacted file tree graph

@@           Coverage Diff           @@
##             main    #1506   +/-   ##
=======================================
  Coverage   99.81%   99.81%           
=======================================
  Files         139      139           
  Lines       11701    11715   +14     
=======================================
+ Hits        11679    11693   +14     
  Misses         22       22
Impacted Files Coverage Δ
simulator/func_sim/alu.h 100.00% <100.00%> (ø)
simulator/risc_v/riscv_instr.cpp 100.00% <100.00%> (ø)
simulator/risc_v/t/unit_test.cpp 100.00% <100.00%> (ø)

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