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MIPT-ILab / mipt-mips

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
http://mipt-ilab.github.io/mipt-mips/
MIT License
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Added sext.b instruction support #1510

Closed Aleksey2509 closed 2 years ago

Aleksey2509 commented 2 years ago

Added signed extend of least significant byte instruction Opcode: 1100100

This instruction sign-extends the least-significant byte in the source to XLEN by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.

X(rd) = EXTS (X(rs)[7 . . 0]);

pavelkryukov commented 2 years ago

Have you followed instructions to build and run tests? Because the tests fail now.

codecov[bot] commented 2 years ago

Codecov Report

Merging #1510 (152c5d9) into main (ae62508) will increase coverage by 0.00%. The diff coverage is 100.00%.

Impacted file tree graph

@@           Coverage Diff           @@
##             main    #1510   +/-   ##
=======================================
  Coverage   99.81%   99.81%           
=======================================
  Files         139      139           
  Lines       11735    11747   +12     
=======================================
+ Hits        11713    11725   +12     
  Misses         22       22
Impacted Files Coverage Δ
simulator/func_sim/alu.h 100.00% <100.00%> (ø)
simulator/risc_v/riscv_instr.cpp 100.00% <100.00%> (ø)
simulator/risc_v/t/unit_test.cpp 100.00% <100.00%> (ø)

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