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MIPT-ILab / mipt-mips

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
http://mipt-ilab.github.io/mipt-mips/
MIT License
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Add option to enable unified pipeline #463

Open pavelkryukov opened 6 years ago

pavelkryukov commented 6 years ago

MIPT-MIPS execution uArch defines 3 three categories of instructions:

  1. Simple arithmetic
  2. Branches/memory instructions
  3. Multi-cycle arithmetic

Currently MIPT-MIPS behaves as follows:

  1. Simple arithmetic is always 4 cycles: (F → D → E → W)
  2. Branches/memory instructions are 5 cycles: (F → D → E → M → W)
  3. Multi-cycle arithmetic latency is defined by 'complex_alu_latency' variable

The objective is to create an 'unified_pipeline' option, which makes simple arithmetic to behave like branch/memory instructions.

pavelkryukov commented 3 years ago

Partially fixed by #1456.