MaistoV / UninaSoC

RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.
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[feature/c_extension] Support C-extension for compressed instructions #13

Open DOTTORM5 opened 1 month ago

DOTTORM5 commented 1 month ago

The current load_binary flows, both HPC and embedded do not support the C-extension, namely it relies on instructions being fixed 32-bit wide.

When loading the binary program into the SoC memory to execute it the endianness is reversed if the loading is performed with a byte granularity greater than 1.

For example, considering the binary instruction at the address 00:

00: AABBCCDD

The bytes order is:

00: AA
01: BB
02: CC
03: DD

But reading the file 4 bytes at a time the entire word is placed into the memory at the address 00, ending in:

00: DD
01: CC
02: BB
03: AA

The endianness is reversed.

This problem affects both xdma_load_binary and jtag2axi_load_binary.

The first solution we adopt is to reverse the 4 bytes before loading them. Of course, this is a temporary solution.

We need to consider how to do it when introducing variable-length instructions, i.e. C-extension.