[feature/hpc/ddr] MIG integration

MaistoV / UninaSoC

RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.

Apache License 2.0

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Open MaistoV opened 1 week ago

MaistoV commented 1 week ago

Ingtegrate DDR MIG in HPC flow for Alveo U250.

TODO: decide whether to merge the this task with CDC or not

DOTTORM5 commented 1 day ago

For this task, the CDC is accomplished by simply using an AXI Clock Converter.
For now, we use one DDR channel, the one nearest to the XDMA (PCIe), to be checked.
For now, we can address only 4 GB of the 16 GB of the single DDR channel (we have just a 32-bit address).