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MaistoV / UninaSoC

RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.
Apache License 2.0
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[feature/debug_module] Integrate RISC-V debug module #22

Open MaistoV opened 1 week ago

MaistoV commented 1 week ago

Add RISC-V debug module and expose it on Xilinx scanchain to make it visible to hw_server