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MaistoV / UninaSoC

RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.
Apache License 2.0
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[bug/core_reset] Fix core reset bug #23

Open MaistoV opened 1 week ago

MaistoV commented 1 week ago

The current reset system only works for the first reset after device programming.

Subsequent resets just halt the system.

Debug is needed.