[feature/hpc/xdma_integration]

[DOTTORM5]

[feature/hpc/xdma_integration] Introduce HPC SoC configuration and XDMA IP

• [Flow] Introduce SoC configuration: HPC and EMBEDDED
• [xilinx] Split IPs in common, hpc and embedded
• [xilinx] Add wrapper module sys_master for XDMA and JTAG2AXI
• [xilinx] Extend uninasoc_axi.sv with port definition
• [xilinx] Add uninasoc_pcie.sv for PCIe-specific macros
• [XDMA] Include XDMA IP
• [XDMA] Support binary loading with XDMA
• [Doc] Update doc for Alveo installation
• NOTE: this PR has a minor workaround for the available number of AXI masters, i.e. axi crossbar does not support just one master (J2A or XDMA) and one slave (BRAM), therefore we just added a second slave BRAM memory generator for now.

[MaistoV]

Add board installation instructions doc for Alveos

[MaistoV]

Add baord installation instruction for Alveos in a .md file (we'll merge it with Nexys-A7-100t afterwards)