Feature/core integration

[Granp4sso]

[Notes] Scheme in uninasoc.sv must be updated [Notes] Scheme in Base_SoC_layout.jpg must be updated. [Notes] We may rethink some of the env_variable names (XILINX ones) since we also integrate custom ips. [Notes] Macros in uninasoc_axi should also include DATAWIDTH for bus array declarations [Units] hw/units contains the rtl files for custom ips. The directory name must match the ip name in hw/xilinx/ips/common. Specifically, it must start with cip (custom IP). custom rtl ip top module should be called wrapper (not mandatory though) and expose a flat interface (mandatory to enable vivado IP packaging). [Flow] hw/xilinx/Makefile: Duplicated variables for XILINX_IPLIST and derived for Custom IPs (CIP_IP_LIST). [Flow] hw/xilinx/Makefile: Changed the _IPLIST* variable to accomodate the new project structure path (see below) [Flow] hw/xilinx/Makefile: Changed XILINX_IP_NAMES to IP_NAMES [Flow] Integration for the custom IP flow [UninaSoC] Integration of RVM Socket

[MaistoV]

As a general comment, CIP/cip might be misleading. I would use COMMON/comon