[feature/core_integration_plus]

MaistoV / UninaSoC

RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.

Apache License 2.0

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[feature/core_integration_plus] #8

Closed Granp4sso closed 1 month ago

Granp4sso commented 1 month ago

[feature/core_integration] Add support for RISC-V cores and custom units.

[xilinx][units] Add support for custom units to export as IPs in Vivado flow.
[Flow] Split Xilinx IP flow in XILINXIP_LIST and CUSTOM_IP_LIST.
[Cores] Add new RVM socket module to wrap RVM cores.
[Cores] Add support for cv32e40p and picorv32 cores.
[Doc] Update doc for new flow.

MaistoV commented 1 month ago

Add some doc in hw/xilinx/README.md#custom-ips on how to import new custom IPs and use the RVM socket

E.g., comments such as which ports are supported by the RVM socket should be in this documentation or

The directory name must match the ip name in hw/xilinx/ips/common. Specifically, it must start with custom_; Use the custom_top_wrapper.sv file in the hw/units/template directory and fill the fetch_sources.sh script to retrieve the rtl sources for the custom IP.