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MiSTer-devel
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EDSAC_MiSTer
FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
MIT License
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rename edsac.sv to EDSAC.sv
#5
birdybro
closed
2 months ago
0
Fix naming scheme and file structure
#4
birdybro
closed
3 years ago
0
Primes on EDSAC
#3
Phi-Ho
opened
3 years ago
6
Quartus Prime (18.1) Analysis & Synthesis was unsuccessful
#2
Phi-Ho
opened
3 years ago
7
Teletype is one character too narrow
#1
rhester72
opened
4 years ago
0