Minres / TGC-VP

The Scale4Edge ecosystem VP
Apache License 2.0
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c-plus-plus c-plusplus riscv systemc

TGC-VP

The Scale4Edge ecosystem VP using VP-VIBES peripherals.

This VP is based in MINRES TGC series cores and uses CoreDSL to generate the concrete ISS of a particular ISA + extensions. The generator approach makes it very flexible and adaptable. Since the CoreDSL description is used to generate RTL as well as verification artifacts it provides a comprehensive and consistent solution to develop processor cores.

Ultra Quick start

Using gitpod you can run the VP in the cloud. Just visit Gitpod.io and follow the instructions. After the build finished you can run


build/src/tgc-vp -f fw/hello-world/prebuilt/hello.elf

or use ctest:


cd build
ctest

You will see on console the prints of the hello world firmware at fw/hello-world/hello.c

Open in Gitpod

Quick start

To rebuild the firmware you need to install a RISC-V toolchain like https://github.com/riscv/riscv-tools.

Windows/Visual Studio build

TGC-VP supports VS2019/MSVC 16 and has been tested only with this version

Prerequisites

You need to have to following installed:

build step

Create a project at the location of the git workarea. This can be done


devenv <path to checkout>

The build steps are as described in the VS documentation for CMake based projects.