FEATURE: Compile data for VHDL expressions

MyersResearchGroup / LEMA

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FEATURE: Compile data for VHDL expressions #34

Open buggsley opened 7 years ago

buggsley commented 7 years ago

Expressions for conditions in VHDL flow control statements are only supported for "=" and "!=". Relational operators such as "<=" or ">=" are not supported. For the supported data expressions, they are compiled into bit extractions on LPN enabling conditions, and the comparison is done on each bit individually. It would be nice to add support to compile the relational operations directly on the data.

buggsley commented 7 years ago

Relational operators ">" and "<" are supported only on single-bit slicing of a std_logic_vector. It would not work for larger bit slice.