Nripench VSD_5_DAYS_TCL_WORKSHOP issues - Githubissues

Nripench / VSD_5_DAYS_TCL_WORKSHOP

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#3 Geetima2021 opened 1 year ago
0
Verilog files not available

#2 Geetima2021 opened 1 year ago
1
osu018_stdcells.lib is missing

#1 Geetima2021 opened 1 year ago
0