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OpenXiangShan
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HuanCun
Open-source high-performance non-blocking cache
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fix(TP): fix XS compiling bug in TPmetaReq/Resp
#181
Ma-YX
closed
2 months ago
0
fix(TP): fix hardcoding issues in Common.scala to support sv48
#180
Ma-YX
closed
2 months ago
0
perf: use perfUtils in `Utility`
#179
Tang-Haojin
closed
4 months ago
0
update CI: use correct tl-test branch
#178
Ivyfeather
closed
5 months ago
0
MSHR: fix a dual-core bug when ReleaseData nests the Probe
#177
sumailyyc
closed
5 months ago
0
configs: Use MaxHartIdBits for hartIdLen
#176
cyyself
closed
6 months ago
0
SRAM: use the clock gating cell from utility
#175
xiaokamikami
closed
6 months ago
0
FIX: bufIdx width should increase after #SinkCbufBlocks increase
#174
Ivyfeather
closed
7 months ago
0
configs: correct MaxHartIdBits
#173
cyyself
closed
7 months ago
0
Kunminghu update bug fixing
#172
Ivyfeather
closed
7 months ago
0
Update bug fixing
#171
Ivyfeather
closed
7 months ago
0
Update misc fixes to kunminghu branch
#170
Ivyfeather
closed
8 months ago
0
Update the clock gating primitive for VCS
#169
Tang-Haojin
closed
8 months ago
0
add some comments
#168
Frankslu
closed
8 months ago
0
init s2_d s3_d in SourceD.scala
#167
SpinEch0
closed
7 months ago
1
An initial version of skew-associative HuanCun
#166
sumailyyc
closed
10 months ago
0
An initial version of skew-associative HuanCun
#165
sumailyyc
closed
10 months ago
0
chore: replace deprecated APIs
#164
Tang-Haojin
closed
10 months ago
0
关于TL--CHI协议
#163
changekkk
opened
10 months ago
0
请教Huancun模块如何与DRAMsim集成并仿真测试
#162
JimmyWong1998
closed
8 months ago
0
Directory: fix perfCounter bug, match resp_bits with right valid and replacerInfo
#161
ruiszhang
closed
10 months ago
0
prefetch: fix tp-meta-req way width
#160
eastonman
closed
10 months ago
1
Directory: fix perfCounter bug, match bits with right valid
#159
ruiszhang
closed
10 months ago
0
Bump Utility and init parameter string for palladium
#158
cailuoshan
closed
11 months ago
0
有关TL-test用于TileLink香山核内核间一致性验证问题
#157
charles7098
closed
1 year ago
2
关于TileLink协议
#156
changekkk
closed
11 months ago
6
prefetch: tp-meta supports hartid-tagged hit comparison
#155
wakafa1
closed
1 year ago
0
prefetch: tp-meta supports multi-core
#154
wakafa1
closed
1 year ago
0
implement and setup TP meta
#153
wakafa1
closed
1 year ago
0
请教关于缓存中T权限的设计
#152
user-stu-l
opened
1 year ago
2
XSPerfAccumulate: change magicStr
#151
Tang-Haojin
closed
1 year ago
6
HuanCun: replace `chisel3.experimental.IO` with `chisel3.IO`
#150
Tang-Haojin
closed
1 year ago
0
build.sc: separate build and common dependencies
#149
poemonsense
closed
1 year ago
0
Bump Mill 0.11.1, Scala 2.13, and Chisel 3.6.0
#148
poemonsense
closed
1 year ago
0
Bump Chisel and rocket-chip
#147
poemonsense
closed
1 year ago
0
Log: remove unexpected `LogPerfHelper` when `RELEASE=1`
#146
Tang-Haojin
closed
1 year ago
0
chore: remove deprecated brackets, APIs, etc.
#145
Tang-Haojin
closed
1 year ago
0
Update the clock gating primitive for Verilator v5.0
#144
poemonsense
closed
1 year ago
0
top-down: do not use boring utils
#143
Tang-Haojin
closed
1 year ago
0
log: use XMR instead of boring utils for logging
#142
Tang-Haojin
closed
1 year ago
0
L3 pf support
#141
wakafa1
closed
1 year ago
0
reqsource: enrich prefetch reqsources
#140
wakafa1
closed
1 year ago
0
utility: use unified `MemReqSource`
#139
Tang-Haojin
closed
1 year ago
0
[tmp] MSHR: for 1 client, we just let probeack_last be sink_c_resp_valid
#138
Ivyfeather
closed
1 year ago
0
MSHR & SourceD: add hitLevelL3toL2 function in L3
#137
ruiszhang
opened
1 year ago
0
MSHR & SourceD: add hitLevelL3toL2 function in L3
#136
ruiszhang
closed
1 year ago
0
MSHR & SourceD: add hitLevelL3toL2 function in L3
#135
ruiszhang
closed
1 year ago
0
Merge bug fixing commits into master branch
#134
wakafa1
closed
1 year ago
0
basic L2 to L3 isHit funcion in HuanCun
#133
ruiszhang
closed
1 year ago
0
请教有关多核原子操作的问题
#132
user-stu-l
closed
1 year ago
1
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