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QianfengClarkShen
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Tbps_CRC
A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
MIT License
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Slow simulation performance
#4
iwaniwaniwan012
closed
9 months ago
3
Not properly working, when data bus not multiple of 2
#3
iwaniwaniwan012
closed
1 year ago
2
Merge pull request #1 from QianfengClarkShen/main
#2
QianfengClarkShen
closed
2 years ago
0
Create LICENSE.md
#1
QianfengClarkShen
closed
2 years ago
0