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RAPcores
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rapcores
Robotic Application Processor
http://rapcores.org/rapcores/
ISC License
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[nix] make docs=false default in shell
#230
sjkelly
closed
2 years ago
1
Phase angle interface on RAPbo and step input on DualH
#229
sjkelly
opened
3 years ago
2
Vector Execution Model Documentation
#228
sjkelly
opened
3 years ago
0
remove Logic Analyizer macro interface, in favor of dot access idiom
#227
sjkelly
closed
3 years ago
0
WIP: SPI Transfer Improvements
#226
sjkelly
opened
3 years ago
1
Sjk/regions4
#225
sjkelly
closed
3 years ago
0
Some Next Gen Tooling
#224
sjkelly
closed
3 years ago
0
[nix] move npm derivations to external repo, others TBD
#223
sjkelly
closed
3 years ago
0
Move out Nix Derivations
#222
sjkelly
opened
3 years ago
1
WIP: Implement Reserved Memory Regions and Document
#221
sjkelly
closed
3 years ago
0
[ci] trigger on push and pull
#220
sjkelly
closed
3 years ago
0
Use TerosHDL for Internal Documentation
#219
sjkelly
closed
3 years ago
0
Register Layouts and Parametrics: Blocked Regions
#218
sjkelly
opened
3 years ago
5
Rework docs dependencies
#217
sjkelly
closed
3 years ago
0
Nix improvements
#216
sjkelly
closed
3 years ago
0
Fixed point scheme
#215
sjkelly
closed
3 years ago
1
WIP: Symbiflow/Quicklogic Support
#214
sjkelly
opened
3 years ago
0
[reginit] fix false positives
#213
sjkelly
closed
3 years ago
0
Register Mapping
#212
sjkelly
closed
3 years ago
2
register step/dir/en inputs, closes #117
#211
sjkelly
closed
3 years ago
0
[nix] update stable channel to 21.05
#210
sjkelly
closed
3 years ago
1
[NFC] Registered Outputs
#209
sjkelly
closed
3 years ago
0
Merge in librapcores
#208
sjkelly
closed
3 years ago
0
Initialize fixed point scheme
#207
sjkelly
closed
3 years ago
0
Carry Chains and Fixed Point for mixed mode controls
#206
sjkelly
closed
3 years ago
1
Register Map
#205
sjkelly
closed
3 years ago
6
Minimal SV enable
#204
sjkelly
closed
3 years ago
0
Synth-time cosine table generator
#203
sjkelly
closed
3 years ago
0
Three Phase SVM Alignment
#202
sjkelly
opened
3 years ago
2
SPI Parametrics Spring Cleaning
#201
sjkelly
closed
3 years ago
0
RFC: Enable System Verilog
#200
sjkelly
closed
3 years ago
0
[iverilog] Wall
#199
sjkelly
closed
3 years ago
0
QA Update, Revised
#198
sjkelly
closed
3 years ago
1
init gray code utils
#197
sjkelly
closed
3 years ago
0
CI adjustments, drop Verilator linting
#196
sjkelly
closed
3 years ago
2
Sjk/misc1
#195
sjkelly
closed
3 years ago
0
WIP Address FSM Metastability
#194
sjkelly
closed
3 years ago
1
[spi] fix preload issue
#193
sjkelly
closed
3 years ago
0
WIP: CRC4
#192
sjkelly
opened
3 years ago
0
SPI Error Correction
#191
sjkelly
opened
3 years ago
1
VFD Starting Coils - Observations
#190
sjkelly
closed
3 years ago
1
Apply Microsteps as a denominator rather than quotient
#189
sjkelly
closed
3 years ago
1
[svm] initial stubout for three phase support
#188
sjkelly
closed
3 years ago
0
Upduino3, PLL, DDA changes
#187
sjkelly
closed
3 years ago
1
Apply PLL Clock in Nextpnr
#186
sjkelly
opened
3 years ago
1
tag some wires with onehot attribute -> better nextpnr frequency
#185
sjkelly
closed
3 years ago
0
WIP: Fixes for telemetry workbench
#184
sjkelly
closed
3 years ago
0
Encoder Velocity and Acceleration Estimates
#183
sjkelly
opened
3 years ago
0
Current model
#182
sjkelly
closed
3 years ago
0
ALERT/WIP: Verilator Width Linting was incorrectly reenabled
#181
sjkelly
closed
3 years ago
0
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