TCL_Workshop_Basic-to-advance

TCL_scripting #VSD_learning #verilog #VLSI #Verification #YOSYS #Opentimer #Scripting_language

TCL Workshop_5 DAYS: Learning from Basic of TCL basics to Advance Scripting Techniques in VLSI. IN this workshop we are going to learn to build a user Interface which will convert the constraits in .csv file to sdc format. With help of Tools Yosys and Opentimer, This user interface will generate a detailed report of the synthesized netlist and prelayout timing report. TCL is widely used in VLSI industry for processing synthesis results, timing reports, automate the physical design flow such as floorplan, placement, and routing. Tcl stands for Tool Command Language. A command follow the instructions given and generate output as example, output a string, compute a math expression, or display a widget on the screen. This strong language can creäte everything into the frame of a command, even programming constructs.

DAY 1: Inception of the TCL workshop

First understand the task and then break it to the many subtasks to learn step by step and generate the detailed report, which will be our Final output of the task.

First Task: Create a command TCLbox(any name) and .csv file from UNIX shell to TCL script. This task has three scenarios to run here which are included in this first task to create a command the TCLbox and work on .csv file Three scenarios are here given below to understand the user behaviour in different mode.

First scenarios when user do not provide the .csv file:

screenshot is given below:

Second scenarios when user give wrong .csv file which does not exists:

screenshot is given below:

Third scenarios when user ask for help to know more about the usage:

screenshot is given below:

DAY 2: Variable creation and processing constraints from CSV file

First Task has completed than second Task is to Convert all inputs to format [1] &SDC format, pass to synthesis tool ‘Yosys’. To complete this task we need to break down the task into subtask and deep dive into the learning skill mode. Tasks are mentioned one by one here in the snippet to achieve the final outcome of this task.

First subtask is to creat the varibales and convert all the information available into the excel sheet. and make a matrix to make things more simpler and proceed further to create variable. Lets understand with help of screenshot than perform the task on VM>, with completion of the task,it will autocreate the variable.

Now Perform the task on the VM and create variables.give command ./TCLbox openMSP430_design_details.csv here is the outcome of the performing task on VM.

Now checking the existence of files or not. second subtask is to check the all files are existing in the directory or not. With code adding in the tcl file, task has performed on the terminal and screenshot for the same is given below.

on the way to Processing of the constraints openMSP430_design_constraints.csv file here, we have put some puts command to find out the results and data avaiavle in the constraints.csv file. here we have put the return in the scipt to stop at that point and show th results after that we will match this data to the orogonal file existing in the directory.

If we check and open the constraints file, given below snippet here.the given columns and rows are matching here.Clocks[rows,coulmn] are starting from zero Inputs starting from the row 4 outputs starting from the row 27

DAY 3: Clock and Input constraints from the csv file and dump these data into the sdc file.

convert the format[1] & SDC formgat to the format[2] and pass to timing tool Opentimer tool. first look at this blue box and the position of the coulumn here which need to convert into the standard format data.Process the clock and inputs and dump into the .csv file. Now understad the clock latency and work our algorithm to convert this to Industry standared format which is the SDC format

This perticular section of the script dum the process the clocks and dump it into the the .csv file Check the snippet of code here given below When run the scirpt with the command over the terminal: ./TCLbox openMSP430_design_details.csv here is the outcome of the performing task and how the script works on the clock section and dumping on the .csv file.

Now we will open the file and check the necessary constraints are written over or not. give the command over terminal: vim outdir_openMSP430/openMSP430.sdc It can be observe here that the file has written with the clock constraints.

Process the input constraints and dump them in to the .csv file. In this given below search space we need to apply the algorithm ro convert this data into the data which can than pass to the further. inputs constarints in the .csv files are presented here in the given screenshot.

This is the code of script which will process the input constraints and dump it into the .csv file.

!

Now give the command the ./TCLbox openMSP430_design_details.csv and observe how it works:

Now we will open the file and check the necessary constraints are written over or not. give the command over terminal: vim outdir_openMSP430/openMSP430.sdc It can be observe here that the file has written with the Input constraints.

Process the output constraints and dump them in to the .csv file. In this given below search space we need to apply the algorithm ro convert this data into the data which can than pass to the tool. OUTPUT constarints in the .csv files are presented here in the given screenshot

This is the code of script which will process the output constraints and dump it into the .csv file.

Now give the command the ./TCLbox openMSP430_design_details.csv and observe how it works:

Now we will open the file and check the necessary constraints are written over or not. give the command over terminal: vim outdir_openMSP430/openMSP430.sdc After scrolling down to the bottom of the document,It can be observe here that the file has written with the OUTPUT constraints.

Day 4: Introduction of YOSYS synthesis and completing the script

Now SDC final file has created, Now last task is to involved here was to perform hierarchy check. This task which reads all the RTL files and elaborates. If either of the sub-module is not found then it will error out.Successfully created the hierarchy check script to be used by the yosys. First scenrio is hierarchy check passed

Second scenrio is hierarchy check fail: to check this task. In verilog directory, instance name changed to omsp_alu_new from omsp_alu. And th tcl script raised a flag and give message as the hirerachy check fail. Screenshot is given below

DAY 5: Advanced TCL scripting

5th day task is here is to generate synthesis.log, convert the SDC constraints to OpenTimer (STA tool) constraints format and generate quality of results (QOR) report from the timing reports generated by OpenTimer tool.

Top level_yosys synthesis script dumping Top level_yosys synthesis script .ys file and dumpeing the script. The code of the same and screenshots of terminal with several "puts" printing out the variables and user debug information are presented here.

Screenshots of terminal

Screenshot of openMSP430.ys

Synthesis finished successfully here and synthesis.log file can be accessed in the outdir directory. check the screenshot here.

It can be observed here that if you access the outdir directort and give the command ls -latr It will show the timing and deatils here as shown below.

Screenshot of openMSP430.synthesis.log

Yosys and OpenTimer tool are different, Now we need to do some changes in the file .synth.v file to make acceptable for openTimer tool.OpenTimer require a different format to read the netlist. The OpenTimer tool dumps lines that contains '*' (asterik symbol) which is not understood.So, it is mandatory to edit the netlist before forwarding it to Opentimer. converting Yosys output netlist to opentimer compatible

here are the screenshots of the difference after conversion open the .synth.v file

open the final.synth.v file and observe the differences.

Next is using the procs to write the .conf file. To do the same basic code and screenshots are given below.

and terminal screenshot

Preparation of rest of .conf & .spef files for OpenTimer STA have done here.for the same the code to write .spef with the current date and time in the spef code and to append the rest of the portion of .conf file.

Code of the same and screenshots of terminal, .conf and .spef are shown below.

Terminal screen_shot

Open MSP430.spef

Open MSP430.conf

STA using OpenTimer Successfully written the code to run STA on OpenTimer and observe the runtime. Screenshot of code is given below

Screenshot of terminal

open MSP430.results

QoR (Quality of Results) Generation:This is the final output for what the whole process and script done for the same The code for QoR generation has given below.

the QOR report generated after post-processing is given below and screenshots of the terminal are shown below.

Conclusion: Complete task to generate the synthesis and STA run_script has done accordingly with required user Interface. The TCL toolbox successfully processes the csv file to generate the sdc constraints and run synthesis and STA to produce the quality of results.

Acknowledgement: KunalGhosh, Co-founder, VSD Corp. Pvt. Ltd. https://www.vlsisystemdesign.com/