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Rutherther
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vhdl-i2c
I2C master and slave implementation in VHDL
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Behavioral models for i2c master, slave
#12
Rutherther
opened
9 months ago
0
Decide when to clear gen start req. When to allow "queueing" requests
#11
Rutherther
opened
9 months ago
0
Clear errors on start_i & run_i
#10
Rutherther
opened
10 months ago
0
Add cannot comply to startstop condition generator
#9
Rutherther
opened
10 months ago
0
Behavioral entities for i2c testing
#8
Rutherther
opened
10 months ago
1
Add possibility to override bus busy without full reset?
#7
Rutherther
opened
10 months ago
1
Add tests for busy prior to resetting
#6
Rutherther
opened
10 months ago
1
Add tests for bus busy
#5
Rutherther
closed
10 months ago
2
Prevent stop before any data received/transmitted
#4
Rutherther
opened
10 months ago
0
Store rw and address until not another start condition
#3
Rutherther
closed
8 months ago
3
Implement timeout when scl generator cannot comply
#2
Rutherther
opened
10 months ago
0
Synchronize reset!
#1
Rutherther
closed
10 months ago
1