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SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
http://peakrdl-regblock.readthedocs.io
GNU General Public License v3.0
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packed structs instead of unpacked structs #62

Closed dale40 closed 1 year ago

dale40 commented 1 year ago

Dear contributors,

I found out that ncverilog raises complaints on unpacked structs.

Here are the log

ncvlog: 15.20-s010: (c) Copyright 1995-2016 Cadence Design Systems, Inc. wire AIDC_LITE_COMP_CFG__in_t cfg_hwif_in; ncvlog: *E,SVUPSL (/home/ScalableArchiLab/HW/AIDCLite/design/sverilog/AIDC_LITE_COMP_TOP.sv,15 50): Unsupported unpacked struct/union functionality: unpacked structure as a net. wire AIDC_LITE_COMP_CFG__out_t cfg_hwif_out;
ncvlog: *E,SVUPSL (/home/ScalableArchiLab/HW/AIDCLite/design/sverilog/AIDC_LITE_COMP_TOP.sv,16 51): Unsupported unpacked struct/union functionality: unpacked structure as a net. 
wire    AIDC_LITE_DECOMP_CFG__in_t  cfg_hwif_in;
                                              |
ncvlog: *E,SVUPSL (/home/ScalableArchiLab/HW/AIDCLite/design/sverilog/AIDC_LITE_DECOMP_TOP.sv,15 50): Unsupported unpacked struct/union functionality: unpacked structure as a net. wire AIDC_LITE_DECOMP_CFG__out_t cfg_hwif_out;
ncvlog: *E,SVUPSL (/home/ScalableArchiLab/HW/AIDCLite/design/sverilog/AIDC_LITE_DECOMP_TOP.sv,16 51): Unsupported unpacked struct/union functionality: unpacked structure as a net.

Can you please pack your structs to stop the error?

amykyta3 commented 1 year ago

This doesn't seem right. I have regularly worked with Cadence's simulator and I have known it to support unpacked structs for nearly a decade. Please check whether you have a modern version of ncsim. SystemVerilog unpacked structs have been broadly supported by many commercial tools for a long time, so it would be inappropriate to change PeakRDL in this instance.

Also, the choice to use unpacked structs is very intentional as it is intended to prevent very common human errors. See #18 for more explanations on why.