SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

http://peakrdl-regblock.readthedocs.io

GNU General Public License v3.0

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asic csr fpga registers systemrdl systemrdl-compiler systemverilog systemverilog-hdl

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.