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### THE CHALLENGE:
Can we provide verilator as an option for CGRA regression testing, as an alternative to existing vcs etc.
### EXECUTIVE SUMMARY of progress so far:
- It turns out that the veri…
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- [x] I have reviewed this project's [contribution guidelines](https://github.com/SystemRDL/systemrdl-compiler/blob/main/CONTRIBUTING.md)
**Describe the bug**
In the following code:
```
`ifd…
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Implement SystemRDL parser.
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I've been trying to run the https://github.com/SystemRDL/RALBot-html/blob/master/example/turboencabulator.rdl example to see if I can get Ordt to parse the same file.
As it appears, Ordt fails to p…
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Hi,
Thank you for this project! I was wondering if you could publish a wheel for it (and all others in the SystemRDL project) to pypy?
I noticed [peakrdl-uvm](https://github.com/SystemRDL/PeakRD…
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SystemRDL 2.0's constraints is the last major feature that is currently unimplemented. Currently, any RDL that contains a constraint block will fail to compile.
* An elaborated constraint is expose…
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Does Corsair support interrupts? I do not mean exactly the same way SystemRDL does, but is there any support for interrupts?
m-kru updated
4 weeks ago
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Does Corsair support different addressing modes? I do not mean byte and word addressing, but `compact`, `regalign` and `fullalign` from SystemRDL nomenclature. Do you always align address space size o…
m-kru updated
4 weeks ago
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If the rdl contains
:
field {
enum xyz{
XXX= 3'b000 {
desc = "XXXXX";
};
YYY= 3'b001 {
desc = "YYYY";
};
encode = xyz;
} bits…
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Follow up to issue #5:
A related issue here is the duplication of the documentation for each array element.
I think the structure of the documentation should be the same for all generators (HTML, …